1. Field of the Invention
The present invention is directed to the field of non-volatile memories. More particularly, this invention relates to a nonvolatile memory array with an arrangement that enables simultaneous read and write operations.
2. Description of the Related Art
Electronic systems typically include processors and memory. The memory will be used to store instructions and/or data. In some systems, non-volatile memory is needed to guarantee that the data is continuously stored even when the system is turned off. One non-volatile memory that is widely used is an EPROM. However, conventional EPROMs cannot be reprogrammed in the field. Thus, many electronic designs use EEPROMS, flash memories or battery-backed SRAM, all of which can be reprogrammed electrically. For devices where costs is a factor, flash memories are preferred because they are less expensive than EEPROMs and battery-backed SRAMs.
One problem with prior flash memories is that they do not provide sufficient random access. For example, prior flash memory devices typically do not allow a processor to perform a read operation while a program or erase operation is underway in the flash memory device. Typically, the processor periodically polls a status register of the flash memory device to detect the end of the program or erase operation before initiating a read operation to the flash memory device.
Unfortunately, the programming and erase cycle times for typical flash memory devices are orders of magnitude greater than acceptable read access times of a random access main memory. Such long latencies associated with programming or erase operations can lock up the operating system and prevent the system from functioning for unacceptably long time intervals if the flash memory is the only memory in the electronic system. Some prior flash memories allow erase suspend operations in order to address this problem. However, such memories typically impose a suspend latency interval of several microseconds before a read operation can be initiated.
Prior systems may employ multiple flash memory devices in an attempt to prevent such operating system lock up. In such systems, the processor usually has read access to one of the flash memory devices while other flash memory devices are undergoing a program or erase operation. However, such systems typically suffer from high cost because multiple flash memory devices are implemented even though the capacity of a single flash memory device may accommodate the particular electronic device.
Another prior art system uses a flash memory in combination with an EEPROM memory. This system allows a read operation of one of the memories while writing to the other. The size of an EEPROM cell is significantly larger than that of a flash memory. Therefore, a device which uses an EEPROM rather than a flash memory will be more expensive. Additionally, because the device includes two different technologies, the device is more complex which results in higher design and manufacturing costs.
Thus, there is a need for an efficient flash memory device that allows simultaneous read and write operations.